The invention pertains to the programmatic extraction of a processor machine description for use in retargeting a compiler.
Explicitly Parallel Instruction Computing (EPIC) processors are a class of processors in which instruction level parallelism (ILP) is explicitly encoded in the processor""s instructions. One form of EPIC processor is a very long instruction word (VLIW) processor. Throughout this document, references to a VLIW processor are intended to broadly encompass EPIC processors.
EPIC processors exploit instruction-level parallelism (ILP) by issuing several operations per instruction to multiple functional units. In creating an EPIC processor, the processor designer creates a structural description of the processor""s datapath and control path. The datapath includes the functional units for executing operations, registers for storing the inputs and outputs of the operations, and the interconnect circuitry (buses, tri-states, multiplexors, etc.) for transferring data between the functional units and register files. The control path provides control signals to the control ports in the datapath based on a program, which is either read from memory or hardwired into the control logic.
In designing an EPIC processor, a number of cost/performance trade-offs need to be made. Each of these trade-offs can have a substantial impact on the overall system cost and performance. Unfortunately, designing a VLIW processor today is a fairly cumbersome manual process which must carefully weigh cost and performance tradeoffs in the light of resource sharing and timing constraints of the given micro-architecture. Optimizations and customizations of the processor, if any, with respect to a set of applications or an application domain must also be determined and applied manually.
The design space of an EPIC processor is enormous and the cost of exploring various designs is so huge that most designers make only incremental modifications to an existing processor design. This approach has the disadvantage that it typically leads to a locally optimal design while ignoring superior designs that may be radically different or require a large amount of quantitative exploration.
Due to the limitations of the manual design process, automated design software provides the potential to explore a wider range of processor designs more effectively. One tool that is helpful in assessing the merits of a particular processor design is a re-targetable compiler. A re-targetable compiler is a type of compiler that can be readily targeted to a processor design by providing sufficient details about the machine to adapt the compiler to that machine. One principle advantage of a re-targetable compiler is that it allows the user to evaluate the merits of a particular machine design while the structural details of the machine are still in flux. This attribute is particularly useful in the design of an application Specific Instruction Set (ASIP) processor. In this context, the re-targeted compiler can generate operation issue statistics for an application program of interest running on a processor that is still being designed.
While in theory, a re-targetable compiler is a useful tool in evaluating a processor design, it is still a cumbersome process to provide the machine details necessary to re-target the compiler. Unless a compiler can be re-targeted efficiently, the advantages it provides may be outweighed by the inefficiencies associated with the re-targeting process.
The invention provides a method for automatic and programmatic extraction of a machine description suitable to re-target a compiler. One aspect of the invention is a method for extracting such a machine description programmatically from a structural description of an EPIC processor""s datapath. This method is implemented as part of a system that automatically generates a structural description of a VLIW processor from an abstract Instruction Set Architecture (ISA) specification of the processor. Within this system, the method may be used to extract a machine description for re-targeting a compiler from the abstract ISA and from a structural representation of the datapath. In addition, it may use additional information about the processor, such as its instruction format or its structural control path design, to further refine the machine description.
The system implementation includes a module referred to as an MDES extractor that programmatically extracts a machine description in a format called MDES. The MDES extractor reads selected data from a machine-readable input specification, including a structural representation of a datapath, and identifies resource sharing constraints among operations in the processor""s opcode repertoire during a structural traversal of the datapath. The MDES extractor constructs a specification of resource constraints in the form of reservation tables that indicate resources required by an opcode as a function of the number of clock cycles elapsed after issuing the opcode. The MDES extractor also gathers other information about the processor""s operations including their input/output (I/O) storage resources where the operands of the operations reside. The resulting MDES provides information to re-target a compiler to the processor being designed.